Clock Network Sizing in Presence of Power Supply Noise

In this paper, we present a novel sequential linear programming approach to the problem of clock network sizing. The original nonlinear programming problem is transformed to a sequence of linear programs, by taking the first order Taylor’s expansion of clock path delay with respect to buffer andwirewidths.The sensitivities of clock path delay, with respect to buffer and wire widths, are efficiently updated for each linear program by applying time domain analysis to the clock network in a divide-andconquer fashion. Our technique takes into account process variation and power supply noise, which have significant impacts on clock skew. We demonstrate experimentally that the proposed technique is not only capable of effectively optimizing clock skew and power consumption, but also able to provide more accurate delay and skew results compared to the traditional approach.